1. Field of the Invention
The present invention relates to a fault simulator for verifying the reliability of a test pattern used for a delivery test of semiconductor circuits such as LSIs.
2. Description of Related Art
A fault simulator is a quality verification apparatus for verifying the degree to which an input vector (test pattern) for the delivery test can screen faulty LSIs in a preshipment test.
FIG. 9 is a block diagram showing a configuration of a conventional fault simulator. In FIG. 9, the reference numeral 100 designates a fault simulator for carrying out the quality verification of a test pattern. It includes a CPU for executing programs for implementing the functions of components which will be described later. The reference numeral 101 designates a stuck-at 0 or 1 fault simulating section constituting a main component of the fault simulator 100. It simulates as to whether a test pattern 104 can screen the stuck-at 0 or 1 fault among the causes of faults of an LSI. The reference numeral 102 designates a netlist consisting of logical connection information on an LSI circuit supplied to the fault simulator 100. The reference numeral 103 designates a list file of fault generation points. It describes information specifying a circuit to which a fault model is to be inserted. The reference numeral 104 designates a test pattern to be verified. It consists of input information for causing the LSI circuit to perform specified operation for the test.
The reference numeral 105 designates a fault detection report file that describes the results the stuck-at 0 or 1 fault simulating section 101 obtains by verifying the test pattern 104 using the netlist 102 and fault generation point list file 103. The reference numeral 106 designates a fault generator for generating a stuck-at 0 or 1 fault model to be incorporated into the fault generation point. The stuck-at 0 or 1 fault model is a fault model for simulating the stuck-at 0 or 1 fault, one of the causes of faults of the LSI circuit. The stuck-at 0 or 1 fault simulating section 101 and fault generator 106 are implemented by a program executed by a computer functioning as the fault simulator 100.
FIGS. 10A and 10B are schematic diagrams illustrating a stuck-at 0 or 1 fault: FIG. 10A illustrates the causes of the stuck-at 0 or 1 fault; and FIG. 10B illustrates output signals in the stuck-at 0 or 1 fault. As illustrated in FIG. 10A, the stuck-at 0 or 1 fault arises when a part of the LSI circuit comes into contact with a power supply or ground. As an example of a normal circuit, an inverter is described here which has an input signal pattern and an output signal pattern as illustrated in FIG. 10B.
When a contact with the power supply takes place at the input side of the inverter as indicated by the symbol A of FIG. 10A, the output signal is stuck at logic level 0 (L level) as indicated by the symbol B of FIG. 10B, which is a stuck-at 1 fault. In contrast, when the input side is grounded, the output signal is stuck at logic level 1 (H level) as indicated by the symbol B, which is a stuck-at 0 fault.
Next, the operation of the conventional fault simulator will be described.
FIG. 11 is a flowchart illustrating the operation of the fault simulator of FIG. 9. The simulation of the stuck-at 0 or 1 fault will be described with reference to FIG. 11.
First, the fault generator 106 in the fault simulator 100 captures the connection information (circuit information) of the LSI circuit from the netlist 102 (step ST101), and extracts from the circuit information a fault generation point to which a virtual fault is to be assigned (step ST102). Subsequently, the fault generator 106 generates the list file 103 of the fault generation point extracted. Here, the fault generator 106 generates a stuck-at 0 or 1 fault model as a fault model that is incorporated into the fault generation point to cause the virtual fault. The conventional fault simulator 100 carries out the test by inserting the fault to the entire LSI circuit (to all the gates and nodes) by using the stuck-at 0 or 1 fault model.
Next, according to the input information fed from the test pattern 104, the stuck-at 0 or 1 fault simulating section 101 in the fault simulator 100 carries out a logic simulation of the normal circuit that will not bring about any fault (step ST103). The stuck-at 0 or 1 fault simulating section 101 keeps the logic simulation results as the expected values of the normal circuit (step ST104).
Subsequently, the stuck-at 0 or 1 fault simulating section 101 incorporates the stuck-at 0 or 1 fault model the fault generator 106 generates into the fault generation point in the LSI circuit read from the fault generation point list file 103, thereby providing a virtual fault (step ST105). Then, the stuck-at 0 or 1 fault simulating section 101 carries out the logic simulation of the faulty circuit (step ST106), and holds the logic simulation results.
Subsequently, the stuck-at 0 or 1 fault simulating section 101 compares the logic simulation results of the normal circuit held at step ST104 with the logic simulation results of the faulty circuit held at step ST106 (step ST107). If the compared result indicates the difference, it means that the test pattern to be verified can detect the fault. Thus, it can confirm the quality of the test pattern. Subsequently, the stuck-at 0 or 1 fault simulating section 101 supplies the compared result to the fault detection report file 105 to be stored (step ST108).
After the foregoing processing has been completed, according to the contents of the fault generation point list file 103, the stuck-at 0 or 1 fault simulating section 101 makes a decision as to whether any other fault generation point is present in the LSI circuit (step ST109). If any other fault generation point is present, the stuck-at 0 or 1 fault simulating section 101 executes the processing from step ST105 to step ST108 for each fault generation point. Subsequently, when no other fault generation point is present at step ST109, it completes the fault simulation processing. Thus, it makes a decision as to whether the fault simulation of the entire circuit has been completed, and continues the fault simulation if necessary.
Next, the causes of the faults of the LSI circuit will be described.
The causes of the faults of the LSI include besides the stuck-at 0 or 1 fault as illustrated in FIGS. 10A and 10B, a delay fault that causes a malfunction because of abnormal operation timing of a circuit, and other faults such as a bridge fault. In the conventional LSI manufacturing process, most of the faults can be verified using the stuck-at 0 or 1 fault model. However, in the ultrafine process in recent years, the delay fault occurs frequently because of the delay through wiring.
FIG. 12 is a diagram illustrating an example of the delay fault, in which a flip-flop (FF) and a timing chart are shown. The flip-flop has a terminal D supplied with a data signal, a terminal T supplied with a clock signal, and a terminal Q producing an output signal. For the convenience sake, the signals corresponding to the terminals D, T and Q are called signals D, T and Q, respectively. FIG. 12 also shows the fluctuations in the input timing of the data signal D along the time axis because of some reasons, which constitute the fault types 1, 2 and 3.
In the timing chart of FIG. 12, the reference symbols S1 and S2 each designate a comparing point of the expected value; and the symbol + designates a normal delay of +5 time units, ++ designates a normal delay of +10 time units, − designates a normal delay of −5 time units, and −− designates a normal delay of −10 time units.
It is unlikely that a semiconductor circuit such as an LSI includes only a flip-flop circuit. Thus, it is natural to assume that the flip-flop is connected to the next circuit. In this case, the signal causing a problem of the entire circuit is the output signal Q. In the example of FIG. 12, it is assumed that no malfunction takes place when the output signal Q operates as in the normal circuit between the time S1 and S2.
Considering these conditions, the fault types will be described. As for the fault type 1, the data signal D arrives with a delay of 5 time units (time unit in the simulation). In this case, the data signal D rises simultaneously with the clock signal T, and hence the operation of the flip-flop circuit is undetermined. Thus, the output signal Q has a problem such as Q(case 1) or Q(case 2). In other words, although the output signal Q(case 1) makes a correct signal transition as in the normal circuit, the output signal Q(case 2) is stuck to the L level.
In the fault type 2, the data signal D arrives with a delay of 10 time units so that the output signal Q has a problem of being unable to make any transition. Finally, in the fault type 3, although the data signal D arrives 5 time units earlier, the output signal Q makes a correct transition between the time S1 and S2, and the circuit operates normally. Thus, it often occurs that the circuit cannot operate normally because of the fluctuations in the timing of the signal transmission. Therefore a fault simulator that can verify the delay fault is necessary.
With the foregoing configuration, the conventional fault simulator lacks the function of generating a delay fault model for considering the effect of the delay. Thus, it has a problem of being unable to verify the test pattern as to whether it can detect a fault due to the timing fluctuations in the signal transmission.
More specifically, semiconductor circuits such as LSIs fabricated through the ultrafine process of recent years have a lot of faults due to the delay through wiring. Accordingly, it is necessary to check whether the test pattern for the delivery test can detect the fault due to the delay correctly or not. However, the conventional stuck-at 0 or 1 fault model, which cannot take account of the timing fluctuations in the signal transmission, cannot verify the test pattern in terms of the fault due to the delay.
In addition, the conventional fault simulator 100 inserts the fault model to the entire LSI circuit (to all the gates and nodes). As a result, the fault simulation time increases enormously with an increase in the circuit scale of the LSI circuit. This offers a problem of being unable to carry out practical fault simulation. In such a case, it is necessary to reduce the points subjected to the fault simulation in the LSI circuit.